Basic principle of LDO LDO is the abbreviation of Low Dropout Regulator, which means low dropout linear regulator. Low dropout refers to the low value of input voltage to output voltage. The differential pressure of traditional linear regulator is up to 2V, while the differential pressure of LDO is only a few hundred mV. Linear means that PMOS is basically in linear working state (the traditional linear regulator is PNP principle and also works in linear amplification state).
The voltage regulator means that within the normal VIN range, the output VOUT is stabilized at a fixed value, which is the voltage value we want. For example, if the VIN is 3~4.4V, the VOUT always keeps 2.7V output.
The following figure is a simple LDO principle block diagram:
LDO is a negative feedback system. When VOUT increases, R2 voltage increases, amplifier output voltage increases, and PMOS VGS voltage decreases. In this way, PMOS output current and voltage decrease. All LDOs have the same negative feedback principle. We often compare LDO with DCDC. Their principles and characteristics are very different: LDO is simple, power is small, efficiency is low, and noise is very low. DCDC is complex, with large power, high efficiency and high noise. To highlight, LDO has a very good noise isolation effect. The specific indicator is PSRR, which represents the ratio of output noise to input noise. In some noise sensitive circuits, such as ADC, DAC, camera sensor analog voltage, LDO must be selected, and it is the LDO with high PSRR, not DCDC. Some key technical indicators of LDO are explained below.
To understand the key parameters of LDO, take TOSHIBA's TCR3DG series LDO as an example to explain the parameters and indicators of LOD. This series of LDOs are widely used in the mobile phone industry. 2.1 Drop out Voltage refers to the minimum voltage difference between VIN and VOUT when the VOUT output voltage and current are guaranteed. This differential pressure can be understood as the voltage drop of LDO output current on PMOS. PMOS has on resistance. Assuming VIN=3.4V, VOUT=3.2V and output current of 300mA, the internal resistance of PMOS can be calculated as
LDO must meet the pressure difference requirements, but the pressure difference is not a fixed value, which is related to the size of IOUT. The figure below shows the relationship curve between the output current of LDO with VOUT=1V and the differential pressure requirement. It can be seen that the smaller the output current is, the smaller the differential pressure requirement is. The smaller the differential pressure is, the higher the efficiency of LDO is. Therefore, try not to let the LDO work at a high current state close to the limit, otherwise the efficiency is very low, the LDO heats seriously and is easy to burn. 2.2 Efficiency LDO efficiency is defined as follows: In fact, IOUT and IIN are basically equal, because IIN has more IGNDs than IOUT, and the current is very small, which can be almost ignored. Therefore, the efficiency formula is simplified as follows. LDO can be simply regarded as a voltage stabilizing pipe. The smaller the differential pressure, the higher the efficiency of LDO. 2.3 Quiescent current (IQ) Quiescent current is the current required for LDO internal circuit power supply when the external load current is 0. The internal circuit includes a bandgap reference voltage source, an error amplifier, an output voltage divider, and over-current and over-temperature detection circuits. This current flows out from the GND of LDO.
Quiescent current is greatly affected by temperature and input voltage. High performance ADI brand LDO may make the quiescent current insensitive to temperature and voltage. The following two figures show the curve of a common LDO quiescent current versus VIN and temperature. The quiescent current is generally at uA and nA levels at room temperature. When the output current increases, the quiescent current IQ at this time is called IGND. For some high-power LDOs, IGND also reaches the level of mA. Most LDOs have very small IQ, which is an important indicator of their own consumption under low load conditions. The smaller the IQ, the better. In the field of consumer electronics, low IQ is conducive to longer battery life, and low IQ value is particularly important. 2.4 After the output enable pin ENn of the LDO is pulled down, VOUT=0V, the current consumed on the VIN is the cut-off current IQ (OFF). The turning off current shall not exceed several uA at most.
2.5 Load transient response
The change rate of output voltage VOUT when the load current IOUT step changes. It is related to the capacitance value of the output terminal, the ESR of the capacitance, the gain bandwidth of the LDO control loop, and the magnitude and rate of load current changes. As mentioned at the beginning of the article, LDO is a negative feedback loop. The greater the phase margin, the better the transient response of the load.
Original link: https://blog.csdn.net/AirCity123/article/details/104213243
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